1. Field of the Invention
The present invention relates to an erasing method in a nonvolatile semiconductor memory device to improve the write/erase endurance which may result from trapping of electrons in a tunnel oxide layer.
2. Description of the Related Art
FIG. 1 is a cross sectional view showing the structure of a memory cell. As shown in FIG. 1, a drain region 3 and a source region 4 are selectively formed at the surface of a semiconductor substrate 7. Also, a tunnel oxide layer 5 and a floating gate 2 are formed on a bridge area of the semiconductor substrate 7 between the drain region 3 and the source region 4. A control gate 1 is formed on the floating gate 2 via an interface layer 6 made of a polycrystalline silicon material.
A method of erasing memories in such memory cells is disclosed in Japanese Patent Application Laid-open No. 4-105368. FIG. 2 is a diagram showing a conventional method of erasing memories in the memory cell. It is assumed in FIG. 2 that the voltage applied to the drain region 3 is Vd, the voltage applied to the control gate 1 is Vcg, and the voltage applied to the source region 4 is Vs.
For writing data, for example, 12 V of the voltage is applied to the control gate 1 while 5 V of the voltage is applied to the drain region 3 with the source region 4 being grounded. At the time, electrons migrating from the source region 4 to the drain region 3 are accelerated by a high intensity of electric field developed adjacent to the drain region 3. Some of electrons are drawn by a vertical component of the electric field and doped over a barrier of the tunnel oxide layer 5 into the floating gate 2.
In a memory erasing action shown in FIG. 2, for example, while the drain region 3 is kept at a floating state, the control gate 1 is loaded with a constant voltage pulse of -11 V and the source region 4 is loaded with 4 V of a constant voltage pulse. As the high electric field runs across the tunnel oxide layer 5, electrons are drawn from the floating gate 2 via the tunnel oxide layer 5 to the source region 4 by the effect of Fowler-Nordheim (FN) tunneling.
In the conventional memory erasing method, while the drain source 3 is at a floating state, the control gate 1 is loaded with a negative constant voltage pulse and the source region 4 is loaded with a positive constant voltage pulse for a period of 3 msec.
However, the conventional memory erasing method has a problem that some electrons are trapped in the tunnel oxide layer 5 by a high electric field stress and will result in decrease of the gate current. As the gate current is decreased, the write/erase endurance will be degraded. For example, the nonvolatile semiconductor memory device is used in place of a magnetic memory device such as a hard disk drive. Although the number of rewriting actions is desired about 100,000, the conventional memory erasing method may provide as small as 10,000 times of rewriting actions.